The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Nov. 15, 2013
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Jung Hyuk Yoon, Icheon-si, KR;

Yoon Jae Shin, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/16 (2013.01); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01);
Abstract

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.


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