The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Dec. 07, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ramesh Raghavan, Narsingi, IN;

Balaji Jayaraman, Bangalore, IN;

Janakiraman Viraraghavan, Bangalore, IN;

Thejas Kempanna, Bangalore, IN;

Rajesh Reddy Tummuru, Bangalore, IN;

Toshiaki Kirihata, Poughkeepsie, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/062 (2013.01); G11C 5/147 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 11/5621 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01);
Abstract

A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.


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