The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2017
Filed:
Sep. 19, 2005
Haeng-won Park, Seongnam-si, KR;
Seung-hwan Moon, Yongin-si, JP;
Nam-soo Kang, Ansan-si, KR;
Sung-jae Moon, Seoul, KR;
Sung-man Kim, Seoul, KR;
Seong-young Lee, Seoul, KR;
Yong-soon Lee, Cheonan-si, KR;
Haeng-Won Park, Seongnam-si, KR;
Seung-Hwan Moon, Yongin-si, JP;
Nam-Soo Kang, Ansan-si, KR;
Sung-Jae Moon, Seoul, KR;
Sung-Man Kim, Seoul, KR;
Seong-Young Lee, Seoul, KR;
Yong-Soon Lee, Cheonan-si, KR;
SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;
Abstract
A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.