Goa circuit of reducing power consumption

Abstract

The present invention provides a GOA circuit of reducing power consumption. In the GOA unit circuit of the Nth stage, the twenty-second thin film transistor (T) of the pull-up module () is controlled by the twenty-first thin film transistor (T) of the second pull-up controlling and transmission module () to output the constant high voltage level (VDD) to the scan driving signal (G(N)) for reducing the parasitic capacitance of the clock signal, lowering the voltage level of the clock signal, easing the loading of the clock signal, and thus, to reduce the power consumption of the GOA circuit; the clock signal (CK(m)) is outputted to the stage transfer signal (ST(N)) through the twenty-first thin film transistor (T), and the stage transfer signal (ST(N)) is employed for the transmission of the signal and the backward feedback to reduce the loading of the scan driving signal, and enhance the propulsive force of the scan driving signal, and the normal function of the GOA circuit can be ensured; and the forty-first thin film transistor (T) is added in the pull-down holding module () to pull down the stage transfer signal (ST(N)) for preventing the electrical leakage of the twenty-second thin film transistor (T).