The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2017
Filed:
Jun. 12, 2015
21, Inc., San Francisco, CA (US);
Veerbhan Kheterpal, Santa Clara, CA (US);
Daniel Firu, San Jose, CA (US);
Nigel Drego, San Francisco, CA (US);
21, Inc., San Francisco, CA (US);
Abstract
Circuit design equipment may design logic for a circuit. The design equipment may discover optimized design constraints and an optimized clock signal frequency for the circuit. The design equipment may output the discovered optimized clock signal frequency and design constraints to circuit fabrication equipment for fabricating the corresponding circuit. The design equipment may discover the optimized clock signal frequency and design constraints by populating a cost function with different clock signal frequencies and different design constraint values. The cost function may be, for example, a multi-dimensional surface. The design equipment may identify a global minimum of the cost function and may identify the clock signal frequency and design constraint values that correspond to the global minimum as the optimized clock frequency and optimized design constraints to provide to circuit fabrication equipment. The fabrication equipment may fabricate the circuit to implement the optimized design constraint values and clock frequency.