The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Feb. 16, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Young-Kyun Jeong, Hwaseong-si, KR;

Jung-Hoon Chun, Seoul, KR;

June-Hee Lee, Yongin-si, KR;

Won-Ho Choi, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 13/4068 (2013.01);
Abstract

A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.


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