The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Jan. 06, 2015
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Yutong Hu, Guangdong, CN;

Peng Du, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 21/66 (2006.01); H01L 21/77 (2017.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); G01R 31/28 (2013.01); H01L 21/77 (2013.01); H01L 22/32 (2013.01); H01L 27/12 (2013.01); H01L 29/78672 (2013.01);
Abstract

The disclosure is related to a method for forming a test pad between adjacent transistors regions, comprising forming a plurality of transistor regions in an array on a glass substrate, wherein each of the transistor region comprises a first transistor region and a second transistor region arranged oppositely; and forming a plurality of test pads between the first transistor region and the second transistor region. The disclosure is further related to a method for array test on the adjacent transistor regions using the test pad formed by the above method. A common test pad formed between the adjacent transistor regions of each transistor region group is employed by the disclosure to perform array test on the adjacent transistor regions. Thus the size of the adjacent fringe region of each transistor region may be reduced to facilitate achieving narrow frame of a display.


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