The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Nov. 04, 2014
Applicant:

Harris Corporation, Melbourne, FL (US);

Inventors:

Michael Raymond Weatherspoon, West Melbourne, FL (US);

Louis Joseph Rendek, Jr., Melbourne, FL (US);

Lawrence Wayne Shacklette, Melbourne, FL (US);

Casey Philip Rodriguez, Indialantic, FL (US);

Assignee:

HARRIS CORPORATION, Melbourne, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01); H05K 1/09 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 1/116 (2013.01); H05K 3/4614 (2013.01); H05K 3/429 (2013.01); H05K 2201/0141 (2013.01); H05K 2201/09545 (2013.01); H05K 2203/061 (2013.01); Y10T 29/49117 (2015.01); Y10T 29/49124 (2015.01); Y10T 29/49126 (2015.01); Y10T 29/49155 (2015.01); Y10T 29/49165 (2015.01);
Abstract

A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.


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