The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Apr. 07, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Andy L. Lee, San Jose, CA (US);

Jeffrey T. Watt, Palo Alto, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2006.01); H03K 19/173 (2006.01); G11C 5/00 (2006.01); H01L 27/02 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03K 19/173 (2013.01); G11C 5/005 (2013.01); H01L 27/0207 (2013.01); H03K 19/1736 (2013.01); H03K 19/17784 (2013.01);
Abstract

Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.


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