The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2017
Filed:
Jul. 19, 2016
Freescale Semiconductor, Inc., Austin, TX (US);
Sanjay K. Wadhwa, Noida, IN;
Divya Tripathi, Noida, IN;
FREESCALE SEMICONDUCTOR,INC., Austin, TX (US);
Abstract
A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter.