The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Dec. 01, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Won-Joo Yun, Yongin-si, KR;

Yong Shim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO, LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03K 7/08 (2006.01); H03L 7/085 (2006.01); H03K 5/156 (2006.01);
U.S. Cl.
CPC ...
H03K 7/08 (2013.01); H03K 5/1565 (2013.01); H03L 7/085 (2013.01);
Abstract

An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal. The delay control circuit is configured to generate the delay control code based on the clock signal and the first output clock signal.


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