The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2017
Filed:
Dec. 12, 2014
Applicant:
Shanghai Jiao Tong University, Shanghai, CN;
Inventors:
Guojie Li, Shanghai, CN;
Xiuchen Jiang, Shanghai, CN;
Keyou Wang, Shanghai, CN;
Lin Feng, Shanghai, CN;
Bei Han, Shanghai, CN;
Lijun Hang, Shanghai, CN;
Assignee:
Shanghai Jiao Tong University, Shanghai, CN;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 7/23 (2006.01); G06F 17/10 (2006.01); G06F 17/50 (2006.01); H02M 1/088 (2006.01); H02M 7/49 (2007.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 7/23 (2013.01); G06F 17/10 (2013.01); G06F 17/50 (2013.01); G06F 17/5063 (2013.01); H02M 1/088 (2013.01); H02M 7/49 (2013.01); H02M 2001/0054 (2013.01); Y02B 70/1491 (2013.01); Y10T 307/549 (2015.04);
Abstract
A method for designing cascaded multi-level inverters with minimization of large-scale voltage distortion, based on KKT (Karush-Kuhn-Tucker) conditions and with simplified computation of conduction angles, simplifies the computation process, and is conducive to on-line calculation. Meanwhile, its fundamental voltage is adaptive, minimization of total harmonic is realized for cascaded multi-level inverters at high-voltage, and voltage power quality at grid connected nodes is improved.