The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Feb. 18, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Uei-Ming Jow, San Diego, CA (US);

Young Kyu Song, San Diego, CA (US);

Jong-Hoon Lee, San Diego, CA (US);

Xiaonan Zhang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01G 4/33 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 28/86 (2013.01); H01G 4/33 (2013.01); H01L 23/5223 (2013.01); H01L 23/642 (2013.01); H01L 28/60 (2013.01);
Abstract

An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.


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