The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Sep. 24, 2014
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Albert Jan Huitsing, Nijmegen, NL;

Jan Claes, Nijmegen, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/02 (2006.01); H01L 27/082 (2006.01); H01L 23/535 (2006.01); H01L 23/367 (2006.01); H01L 27/12 (2006.01); H01L 21/8222 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); H01L 21/8222 (2013.01); H01L 23/367 (2013.01); H01L 23/535 (2013.01); H01L 27/0259 (2013.01); H01L 27/082 (2013.01); H01L 27/1203 (2013.01); H01L 29/41708 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.


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