The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Feb. 20, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Horst Theuss, Wenzenbach, DE;

Beng Keh See, Melaka, MY;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 24/97 (2013.01); H01L 21/568 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01);
Abstract

In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.


Find Patent Forward Citations

Theuss, Horst. (2017). Chip arrangement and a method of manufacturing a chip arrangement (U.S. Patent No. 9653405). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9653405

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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