Shift register, driving method and gate driving circuit

Abstract

Embodiments of the disclosure provide a shift register, a driving method and a gate driving circuit. In an embodiment, the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor. The shift register is driven by the cooperation of the respective transistors. In the case that the shift register is applied in the gate driving circuit to implement a line-by-line scanning, shift registers corresponding to two adjacent pixel rows are cascaded directly and no inverters are provided following the shift registers corresponding to the respective pixel rows, thereby decreasing the number of transistors in the gate driving circuit, reducing the layout area of the gate driving circuit, and being advantageous for narrowing the border.