The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Nov. 11, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Yuhei Yoshimoto, Hyogo, JP;

Yoshikazu Katoh, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 16/20 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0059 (2013.01); G11C 13/0069 (2013.01); G11C 16/20 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0083 (2013.01);
Abstract

A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.


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Yoshimoto, Yuhei. (2017). Tamper-resistant non-volatile memory device comprising an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, a read circuit that, in operation, selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, and a write circuit that, in operation, performs a write operation corresponding to one of the two values among memory cells (U.S. Patent No. 9653161). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9653161

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