The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Jul. 21, 2015
Applicants:

Lloyd F. Aquino, Marion, IA (US);

John L. Hagen, Marion, IA (US);

Todd E. Miller, Marion, IA (US);

Branden H. Sletteland, Marion, IA (US);

Inventors:

Lloyd F. Aquino, Marion, IA (US);

John L. Hagen, Marion, IA (US);

Todd E. Miller, Marion, IA (US);

Branden H. Sletteland, Marion, IA (US);

Assignee:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/00 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0724 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0683 (2013.01); G06F 11/1008 (2013.01);
Abstract

A system and method for detection and correction of single-bit errors in a multi-core processing resource (MCPR) of an avionics processing system includes a RAM EDAC testing module called by the MCPR health monitor to access EDAC registers of a system-on-chip module coupled to the MCPR and access memory addresses passed by the MCPR health monitor to detect single-bit errors. Single-bit errors detected in memory mapped to the hypervisor are corrected by the RAM EDAC testing module. Single-bit errors detected in memory associated with a partition or core of the MCPR are corrected by the health monitor running on the particular partition or core with which the memory portion is associated. Single-bit errors may be detected in unmapped memory associated with a partition or core by accessing the unmapped memory via a temporary TLB entry.


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