The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Feb. 15, 2016
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Haoqiang Zheng, Mountain View, CA (US);

Lenin Singaravelu, Sunnyvale, CA (US);

Shilpi Agarwal, San Mateo, CA (US);

Daniel Michael Hecht, San Francisco, CA (US);

Garrett Smith, San Francisco, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/455 (2006.01); H04L 12/875 (2013.01); H04L 12/26 (2006.01); H04L 12/927 (2013.01); G06F 13/24 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/45533 (2013.01); G06F 9/5027 (2013.01); G06F 9/5033 (2013.01); G06F 9/5088 (2013.01); G06F 13/24 (2013.01); H04L 43/0894 (2013.01); H04L 43/16 (2013.01); H04L 47/56 (2013.01); H04L 47/801 (2013.01); G06F 9/50 (2013.01); G06F 2009/45575 (2013.01); G06F 2009/45591 (2013.01); G06F 2209/5017 (2013.01);
Abstract

A host computer has one or more physical central processing units (CPUs) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical CPU when the corresponding container is determined to be latency sensitive. The assignment of a process to execute exclusively on a corresponding physical CPU includes the migration of tasks from the corresponding physical CPU to one or more other physical CPUs of the host system, and the directing of task and interrupt processing to the one or more other physical CPUs. Tasks of the process corresponding to the container are then executed on the corresponding physical CPU.


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