The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9652204 B1

PDF
Full Text
Expired
Date of Patent:
May. 16, 2017

Filed:

Oct. 24, 2011
Applicants:

Ravindra Patankar, Phoenix, AZ (US);

Shreyas Iyer, Phoenix, AZ (US);

Sravan Rachamalla, Andhra Pradesh, IN;

Murali Kadeppagari, Karnataka, IN;

Inventors:

Ravindra Patankar, Phoenix, AZ (US);

Shreyas Iyer, Phoenix, AZ (US);

Sravan Rachamalla, Andhra Pradesh, IN;

Murali Kadeppagari, Karnataka, IN;

Assignee:

HONEYWELL INTERNATIONAL INC., Morris Plains, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2006.01); G06F 9/44 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 8/36 (2013.01); G06F 11/3604 (2013.01); G06F 2212/173 (2013.01);
Abstract

Methods and apparatus are provided for building and executing reconfigurable algorithms in on-board environments which require pre-certification of the compiled code, such as avionics, flight control, and military applications. The code execution architecture includes a library of reusable function modules in the form of pre-compiled code blocks; an algorithm execution utility (AEU) for processing a user-assembled string of code blocks; and a customer interface for selecting code blocks, defining their associated parameters and sequence (execution order), structuring inputs and outputs, and for providing the integrated, machine readable application to the AEU at run time. The various sequences, permutations and combinations of functions and their associated parameters, inputs and outputs are pre-approved or certified a priori; consequently, the on-board reconfiguration and execution of complex algorithms may be performed in real time without the need for recoding, verification, or redeployment of the code base.


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