The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Dec. 18, 2013
Applicant:

National Instruments Corporation, Austin, TX (US);

Inventors:

John G. Banaska, Cedar Park, TX (US);

Pablo Limon, Cedar Park, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); G01R 31/28 (2006.01); G01R 19/00 (2006.01); H05K 1/02 (2006.01); G01R 3/00 (2006.01);
U.S. Cl.
CPC ...
G01R 19/0092 (2013.01); G01R 3/00 (2013.01); H05K 1/0219 (2013.01); H05K 1/0268 (2013.01); H05K 2201/09618 (2013.01); Y10T 29/49147 (2015.01);
Abstract

System and methods for use and fabrication of a printed circuit board (PCB). The PCB may include a node and a plurality of rows of vias that may be configured to establish a plurality of current pathways away from the node. The node may be a sensitive node and the plurality of current pathways may reduce leakage current at the node responsive to a signal applied to the node. Each row of the plurality of rows of vias may be offset with respect to adjacent rows of vias in a horizontal plane of the PCB. The PCB may have multiple layers and the node may be on an exterior surface layer or an interior layer. The vias may be mirco-vias, buried-vias, or through-vias.


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