The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Apr. 17, 2014
Applicant:

Agency for Science, Technology and Research, Singapore, SG;

Inventors:

Ilker E. Ocak, Singapore, SG;

Julius Ming Lin Tsai, Singapore, SG;

Navab Singh, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); H01L 25/00 (2006.01); G01C 19/56 (2012.01); G01R 33/00 (2006.01); G01R 33/028 (2006.01); G01P 15/08 (2006.01); G01P 15/125 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0048 (2013.01); B81C 1/00285 (2013.01); G01C 19/56 (2013.01); G01P 15/0802 (2013.01); G01P 15/125 (2013.01); G01R 33/00 (2013.01); G01R 33/0052 (2013.01); G01R 33/0286 (2013.01); H01L 25/00 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0271 (2013.01); B81B 2201/0292 (2013.01); B81B 2203/04 (2013.01); B81B 2207/07 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/0172 (2013.01); G01P 2015/0814 (2013.01); G01P 2015/0828 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An electromechanical device and method of fabrication thereof comprising: providing a first wafer with a circuit arrangement on a first surface thereof and a first electrode on a second surface thereof; forming first and second via structures from the first surface to the second surface of the first wafer, said first via electrically connecting the first electrode with the circuit arrangement; providing a second wafer with a suspended structure on a first surface thereof; forming a second electrode on the suspended structure; forming an interconnect structure on the first surface of the second wafer that electrically connects with the second electrode; bonding the first wafer to the second wafer with the second surface of the first wafer facing the first surface of the second wafer, with the second via structure electrically connecting the circuit arrangement to the interconnect structure, and the first and second electrodes forming a capacitive structure.


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