The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Aug. 15, 2016
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Norbert Egi, Santa Clara, CA (US);

Robert Lasater, Menlo Park, CA (US);

Guangyu Shi, Cupertino, CA (US);

Thomas Boyle, Plano, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/947 (2013.01); H04L 12/24 (2006.01); H04L 12/753 (2013.01); H04L 12/707 (2013.01); H04L 12/933 (2013.01);
U.S. Cl.
CPC ...
H04L 49/25 (2013.01); H04L 41/12 (2013.01); H04L 45/24 (2013.01); H04L 45/48 (2013.01); H04L 49/15 (2013.01);
Abstract

In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.


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