The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Aug. 26, 2014
Applicant:
Glf Integrated Power, Inc., Santa Clara, CA (US);
Inventors:
Stephen W. Bryson, Cupertino, CA (US);
Ni Sun, Sunnyvale, CA (US);
Assignee:
GLF Integrated Power, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/08 (2006.01); H03K 17/16 (2006.01); H02J 9/06 (2006.01); H02J 7/34 (2006.01); H02H 1/04 (2006.01);
U.S. Cl.
CPC ...
H03K 17/161 (2013.01); H02J 7/345 (2013.01); H02J 9/06 (2013.01); H02H 1/043 (2013.01); Y10S 323/908 (2013.01);
Abstract
A fully integrated circuit configuration that can be used to control the power path of a pair of PMOS load switches is described. The circuit also integrates a programmable slew rate for the second PMOS load switch in order to control the power path from the input system voltage (battery or power supply) or from a backup source of power. The integrated circuit configuration also contains a charge pump circuit which can be used to charge the backup source of power to a voltage that is greater than the input voltage.