The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Jan. 19, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Sung-Soo Chi, Gyeonggi-do, KR;

Young-Sik Heo, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); G11C 11/4076 (2006.01); H03K 5/14 (2014.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); H03K 3/037 (2013.01); H03K 2005/00019 (2013.01);
Abstract

A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal.


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