The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Dec. 09, 2015
Applicants:
Shiguo Luo, Austin, TX (US);
Kejiu Zhang, Round Rock, TX (US);
Hang LI, Austin, TX (US);
Inventors:
Assignee:
Dell Products L.P., Round Rock, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/157 (2006.01); H02M 3/158 (2006.01); G06F 1/32 (2006.01); G06F 1/26 (2006.01); H02M 1/36 (2007.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/157 (2013.01); G06F 1/26 (2013.01); G06F 1/32 (2013.01); G06F 1/3206 (2013.01); H02M 1/36 (2013.01); H02M 3/1584 (2013.01); H02M 3/1588 (2013.01); H02M 2001/0006 (2013.01); H02M 2001/0032 (2013.01); H02M 2003/1586 (2013.01); Y02B 70/1466 (2013.01); Y02B 70/16 (2013.01);
Abstract
Methods and systems are disclosed that may be employed to improve efficiency of smart integrated power stages (IPstages) of multi-phase VR systems while operating under relatively light, ultra-light, or partial or reduced loads. The disclosed methods and systems may be implemented to improve VR system light load efficiency by providing and enabling reduced power IPstage operating modes in one or more smart IPstage/s of a VR system, and by enabling state transition between IPstage active and reduced power operating modes such as IPstage standby and IPstage hibernation modes.