The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Nov. 13, 2014
Applicants:
Duy VU Pham, Oberhausen, DE;
Kuo Hui Su, Taipei, TW;
Inventors:
Duy Vu Pham, Oberhausen, DE;
Kuo Hui Su, Taipei, TW;
Assignee:
Evonik Degussa GmbH, Essen, DE;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/02271 (2013.01); H01L 23/3171 (2013.01); H01L 27/1225 (2013.01); H01L 29/41733 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); H01L 29/78618 (2013.01);
Abstract
The present invention relates to a novel thin film transistor (TFT) comprising a substrate () with a gate electrode layer () deposited and patterned thereon and a gate insulator layer () deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer () arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer () deposited on the carrier injection layer, and (iii) a semiconductor layer (), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.