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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9647011 B1

PDFFull Text
Date of Patent:
May. 09, 2017

Filed:

Aug. 21, 2014

Thin film transistor array panel and manufacturing method thereof

Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

Jae-Yong Shin, Asan-si, KR;

Woo-Sung Sohn, Seoul, KR;

Hong Min Yoon, Seoul, KR;

Hui Gyeong Yun, Asan-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:

H.C. Park & Associates, PLC

Primary Examiner:

William F Kraig

Assistant Examiner:

Sophia Nguyen

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/146 (2006.01); H01L 27/32 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1262 (2013.01); G02F 1/13452 (2013.01); G02F 1/136204 (2013.01); H01L 21/28008 (2013.01); H01L 21/76802 (2013.01); H01L 23/564 (2013.01); H01L 27/124 (2013.01); H01L 27/1214 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 27/1288 (2013.01); H01L 27/14609 (2013.01); H01L 27/14643 (2013.01); H01L 27/3213 (2013.01); H01L 27/3244 (2013.01); H01L 27/3246 (2013.01); H01L 27/3262 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.

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