The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Dec. 13, 2013
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Ordos Yuansheng Optoelectronics Co., Ltd., Ordos, Inner Mongolia, CN;

Inventors:

Fuqiang Li, Beijing, CN;

Xuelu Wang, Beijing, CN;

Cheng Li, Beijing, CN;

Seong Jun An, Beijing, CN;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/136213 (2013.01); H01L 27/1222 (2013.01); H01L 27/1255 (2013.01); G02F 1/136209 (2013.01); G02F 1/136227 (2013.01); G02F 2201/40 (2013.01); H01L 29/78696 (2013.01);
Abstract

An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes a base substrate, and further includes a metal shield layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer and a pixel electrode layer sequentially formed on the base substrate. At least one first via hole penetrating to the metal shield layer is formed in the interlayer dielectric layer and the gate insulation layer. The source-drain metal layer is formed in the at least one first via hole and on the interlayer dielectric layer having the at least one first via hole.


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