The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Sep. 04, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Sadatoshi Murakami, Yokohama, JP;

Hiroomi Nakajima, Yokkaichi, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 21/336 (2006.01); H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 29/66 (2006.01); H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 27/11578 (2017.01); H01L 21/8234 (2006.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 21/823462 (2013.01); H01L 21/823857 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.


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