The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

May. 13, 2015
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Oliver Haeberlen, Villach, AT;

Walter Rieger, Arnoldstein, AT;

Christoph Kadow, Neuried, DE;

Markus Zundel, Egmating, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01L 31/0304 (2006.01); H01L 21/48 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 21/768 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4871 (2013.01); H01L 21/76879 (2013.01); H01L 29/0626 (2013.01); H01L 29/41766 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01); H01L 29/2003 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of AlGaInN (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) is formed. A second semiconductor layer of AlGaInN (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.


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