The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Mar. 03, 2016
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Srinivasa Raghavan Sridhara, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/417 (2006.01); G11C 5/14 (2006.01); G11C 11/412 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 5/148 (2013.01); G11C 11/412 (2013.01); G11C 11/4074 (2013.01);
Abstract
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.
Sridhara, Srinivasa. (2017). Power gate for latch-up prevention (U.S. Patent No. 9646680). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9646680
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile