The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Oct. 07, 2016
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Norbert Egi, Santa Clara, CA (US);

Robert Lasater, Menlo Park, CA (US);

Thomas Boyle, Santa Clara, CA (US);

John Peters, Sunnyvale, CA (US);

Guangyu Shi, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/24 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 13/32 (2006.01);
U.S. Cl.
CPC ...
G06F 13/24 (2013.01); G06F 13/404 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 13/32 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.


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