The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Jan. 13, 2014
Applicant:

Imagination Technologies, Ltd., Kings Langley, GB;

Inventor:

Jason Meredith, Hemel Hempstead, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2016.01); G06F 12/128 (2016.01); G06F 12/127 (2016.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01);
U.S. Cl.
CPC ...
G06F 12/128 (2013.01); G06F 12/127 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01);
Abstract

Fill partitioning of a shared cache is described. In an embodiment, all threads running in a processor are able to access any data stored in the shared cache; however, in the event of a cache miss, a thread may be restricted such that it can only store data in a portion of the shared cache. The restrictions to storing data may be implemented for all cache miss events or for only a subset of those events. For example, the restrictions may be implemented only when the shared cache is full and/or only for particular threads. The restrictions may also be applied dynamically, for example, based on conditions associated with the cache. Different portions may be defined for different threads (e.g. in a multi-threaded processor) and these different portions may, for example, be separate and non-overlapping. Fill partitioning may be applied to any on-chip cache, for example, a L1 cache.


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