The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Jun. 09, 2014
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Ganesh K. Balachandran, Sunnyvale, CA (US);

Vladimir P. Petkov, San Jose, CA (US);

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); H03K 17/16 (2006.01); G05F 3/16 (2006.01); G05F 3/26 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
H03K 17/16 (2013.01); G05F 3/16 (2013.01); G05F 3/26 (2013.01); G11C 27/02 (2013.01); G11C 27/024 (2013.01); G11C 27/028 (2013.01);
Abstract

A current mirror circuit includes a first transistor connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor, a current source connected to the drain and the gate of the first transistor, the current source being configured to generate a predetermined first output current, a sample and hold circuit having an input connected to the gate of the first transistor, a second transistor connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit, and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency to attenuate bias noise from the first transistor in a second output current from the second transistor.


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