The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2017
Filed:
Jan. 29, 2015
Qualcomm Incorporated, San Diego, CA (US);
Chi-Fan Yung, San Jose, CA (US);
Vishal Gupta, Sunnyvale, CA (US);
Joseph Duncan, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).