The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2017
Filed:
Nov. 06, 2015
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Kazutaka Suzuki, Kanagawa, JP;
Takahiro Korenari, Kanagawa, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01M 10/42 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 23/31 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01M 10/425 (2013.01); H01L 21/823487 (2013.01); H01L 23/3114 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/0696 (2013.01); H01L 29/41741 (2013.01); H01L 29/66477 (2013.01); H01L 29/7813 (2013.01); H01L 21/823418 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.