The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Dec. 15, 2015
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Alain Chantre, Seyssins, FR;

Pascal Chevalier, Chapareillan, FR;

Gregory Avenier, Grenoble, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8249 (2006.01); H01L 27/12 (2006.01); H01L 29/73 (2006.01); H01L 29/732 (2006.01); H01L 29/737 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66272 (2013.01); H01L 21/8249 (2013.01); H01L 27/1203 (2013.01); H01L 29/1004 (2013.01); H01L 29/66234 (2013.01); H01L 29/66242 (2013.01); H01L 29/66265 (2013.01); H01L 29/73 (2013.01); H01L 29/7317 (2013.01); H01L 29/7322 (2013.01); H01L 29/7371 (2013.01);
Abstract

A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.


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