The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Jul. 28, 2015
Applicant:

SK Hynix Inc., Incheon-si, Gyeonggi-do, KR;

Inventors:

Ki Jun Sung, Cheongju-si, KR;

Young Geun Yoo, Icheon-si, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 21/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 23/13 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/96 (2013.01); H01L 25/065 (2013.01); H01L 25/50 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73217 (2013.01); H01L 2224/92144 (2013.01); H01L 2924/141 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1441 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01);
Abstract

Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. The semiconductor package may include a semiconductor chip disposed in the cavity and coupled to chip connectors, the chip connectors of the semiconductor chip inserted into the connection window. The semiconductor package may include a dielectric layer filling the cavity and the connection window and configured to expose end portions of the chip connectors and to substantially cover the semiconductor chip. Related memory cards and related electronic systems are also provided.


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