The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Jan. 15, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Chao Zheng, Shanghai, CN;

Wei Wang, Shanghai, CN;

Junde Ma, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/304 (2006.01); H01L 21/20 (2006.01); H01L 21/66 (2006.01); H01L 21/02 (2006.01); H01L 21/78 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 21/02057 (2013.01); H01L 21/304 (2013.01); H01L 21/306 (2013.01); H01L 21/3065 (2013.01); H01L 21/78 (2013.01); H01L 22/14 (2013.01);
Abstract

A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.


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