The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Sep. 25, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Jun Li, Fremont, CA (US);

Joseph Tzou, Mountain View, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/12 (2006.01); G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 11/413 (2006.01); G11C 11/418 (2006.01); G06F 13/42 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G06F 13/4243 (2013.01); G11C 7/1042 (2013.01); G11C 8/12 (2013.01); G11C 11/413 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.


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