The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2017
Filed:
Sep. 27, 2011
Simon John Craske, Cambridge, GB;
Melanie Emanuelle Lucie Teyssier, Sophia Antipolis, FR;
Nicolas Jean Phillippe Huot, Sophia Antipolis, FR;
Gilles Eric Grandou, Sophia Antipolis, FR;
Simon John Craske, Cambridge, GB;
Melanie Emanuelle Lucie Teyssier, Sophia Antipolis, FR;
Nicolas Jean Phillippe Huot, Sophia Antipolis, FR;
Gilles Eric Grandou, Sophia Antipolis, FR;
ARM Limited, Cambridge, GB;
Abstract
A data processing system () includes memory protection circuitry () storing access control data for controlling accesses to data at memory addresses within a main memory (). An access control cache () may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry () to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache () is storing access control data for a memory access request, then the access control data stored within the access control cache () is used in place of access control data retrieved form the memory protection circuitry (). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.