The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Nov. 06, 2015
Applicant:

Parallel Machines Ltd., Tel Aviv, IL;

Inventors:

Michael Adda, Dimona, IL;

Avner Braverman, Tel-Aviv, IL;

Lior Amar, New Tsiona, IL;

Dan Aloni, Tel Aviv, IL;

Lior Khermosh, Givataim, IL;

Gal Zuckerman, Holon, IL;

Assignee:

Parallel Machines Ltd., Tel Aviv, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/0875 (2016.01); G11C 7/10 (2006.01); G06F 12/0811 (2016.01); G06F 12/1081 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 12/0811 (2013.01); G06F 12/1081 (2013.01); G11C 7/1072 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/283 (2013.01); G06F 2212/452 (2013.01);
Abstract

Described herein are systems and methods to prevent a controller in a DDIO (data direct input output) system from shifting currently-required data out of a cache memory. In one embodiment, a compute element disables caching of some specific addresses in a non-cache memory, but still enables caching of other addresses in the non-cache memory, thereby practically disabling the DDIO system, so that data sets not currently needed are placed in the addresses in the non-cache memory which are not cached. As a result, currently-required data are not shifted out of cache memory. The compute element then determines that the data sets, which formerly avoided being cached, are now required. The system therefore copies the data sets that are now required from addresses in non-cache memory not accessible to cache memory, to addresses in non-cache memory accessible to cache memory, thereby allowing the caching and processing of such data sets.


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