The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Mar. 19, 2015
Applicant:

The Regents of the University of Michigan, Ann Arbor, MI (US);

Inventors:

David T. Blaauw, Ann Arbor, MI (US);

Dennis Sylvester, Ann Arbor, MI (US);

Myungjoon Choi, Ann Arbor, MI (US);

Inhee Lee, Ann Arbor, MI (US);

Taekwang Jang, Ann Arbor, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 3/16 (2006.01); G05F 1/46 (2006.01); G05F 1/575 (2006.01); G05F 3/24 (2006.01);
U.S. Cl.
CPC ...
G05F 3/16 (2013.01); G05F 1/468 (2013.01); G05F 1/575 (2013.01); G05F 3/242 (2013.01);
Abstract

A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.


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