The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Oct. 28, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Fumiya Watanabe, Yokohama, JP;

Mikihiko Ito, Tokyo, JP;

Masaru Koyanagi, Tokyo, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G 7/12 (2006.01); G06G 7/26 (2006.01); H03F 3/45 (2006.01); G11C 7/10 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
H03F 3/4521 (2013.01); G11C 7/1057 (2013.01); G11C 7/062 (2013.01); H03F 2203/45651 (2013.01); H03F 2203/45658 (2013.01);
Abstract

According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits.


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