The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Feb. 27, 2013
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Greg A. Dix, Tempe, AZ (US);

Dan Grimm, Mesa, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7809 (2013.01); H01L 29/41766 (2013.01); H01L 29/0878 (2013.01); H01L 29/456 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.


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