The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Oct. 15, 2013
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Tsung-Hsiung Lee, Taoyuan, TW;

Jui-Chun Chang, Hsinchu, TW;

Shang-Hui Tu, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H01L 29/1083 (2013.01);
Abstract

A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact.


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