The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

May. 09, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Masaki Yamato, Mie-ken, JP;

Takeshi Yamaguchi, Mie-ken, JP;

Shigeki Kobayashi, Mie-ken, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 27/249 (2013.01); H01L 27/2463 (2013.01); H01L 45/1233 (2013.01); H01L 45/1616 (2013.01); H01L 45/1683 (2013.01); H01L 45/04 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01);
Abstract

According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.


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