The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Jun. 16, 2015
Applicant:

E Ink Holdings Inc., Hsinchu, TW;

Inventors:

Kai-Cheng Chuang, Hsinchu, TW;

Chao-Jung Chen, Hsinchu, TW;

I-Hsuan Chiang, Hsinchu, TW;

Assignee:

E INK HOLDINGS INC., Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 35/24 (2006.01); H01L 51/00 (2006.01); H01L 27/12 (2006.01); H01L 51/05 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1218 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 29/41733 (2013.01); H01L 29/78603 (2013.01); H01L 29/78696 (2013.01); H01L 51/0545 (2013.01); H01L 27/3262 (2013.01); H01L 27/3274 (2013.01); H01L 29/786 (2013.01); H01L 2251/5338 (2013.01);
Abstract

A thin film transistor (TFT) substrate includes a substrate which is a flexible substrate, and a TFT structure disposed on the substrate and including a gate layer, a gate insulator layer, a first channel island and a second channel island. The gate layer is disposed on the substrate and including a first gate electrode and a second gate electrode electrically connected to each other. The first and second gate electrodes are parts of the same TFT structure. The gate insulator layer covers the first and second gate electrodes. The first and second channel islands are disposed on the gate insulator layer and respectively correspond to the first and second gate electrodes. The source and drain layer is disposed on the gate insulator layer and next to the first and second channel islands, wherein the source and drain layer partially covers top surfaces of the first and second channel islands.


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