The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Jul. 13, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Satyanarayana Sahu, San Diego, CA (US);

Xiangdong Chen, San Diego, CA (US);

Ramaprasath Vilangudipitchai, San Diego, CA (US);

Dorav Kumar, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H01L 27/11 (2006.01); H01L 27/118 (2006.01); H03K 19/003 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); H01L 27/0266 (2013.01); H01L 27/092 (2013.01); H03K 19/0008 (2013.01); H03K 19/00361 (2013.01); H03K 19/17728 (2013.01); H03K 19/17736 (2013.01); H01L 2027/11811 (2013.01); H01L 2027/11861 (2013.01); H01L 2027/11875 (2013.01);
Abstract

A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.


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